Typically, microprogrammed systems are constructed from a variety of very large scale integrated circuit (VLSI) chips used as building blocks in an architecture which can be divided into two subsections: a control section that supervises the order and decoding of instructions to be executed, and a data processing section which performs the operations called for by the instructions on the data. The control section normally includes a microprogram sequence controller that issues microprogram addresses, and a microprogram memory which contains microinstructions. Each microinstruction includes a plurality of bits to control the elements within the data processing section.
Previous microprogram sequence controllers have been able to address microprogram memories of relatively limited size. One approach to increasing the size of the memory accessible by the controller is to parallel a number of controllers to gain the necessary addressing capability. This is typically referred to as the "bit- or byte-sliced" method. This method, however, entails extensive parallel interconnection of the terminal pins of the controller chips which can increase the cycle time of the controllers, entails a larger package count and higher fabrication and application costs, and requires more physical space for the microprogrammed system. Furthermore, certain on-chip functions are needlessly duplicated, such as the microinstruction decode function present on each controller chip.
Another limitation of previous microprogram sequence controllers is the way in which the last-in first-out stack has been implemented. In one approach, a separate register was used for temporary storage of the top of stack contents so that a PUSH could be accomplished during one instruction cycle. This register simply resulted from the need to stabilize the write address signal to the RAM implementing the stack and the fact that the write might be conditioned on a test of the status of an element within the data processor. Since the total of the time needed for the address signal to stabilize and the time needed to determine the condition signal is greater than the time, usually 50%, of the instruction cycle devoted to instruction execution, the register was employed to hold the word until the next instruction cycle when it could be transferred to the RAM implementing the stack.
In addition, this approach entails deferring until a second instruction cycle the actual writing onto the RAM, thereby assuring a stable write address signal. Thus in this approach, an excess, dedicated register is required, making the controller more complex and costly and PUSHes onto the stack require two instruction cycles, slowing the performance of the controller and ultimately the microprogrammed system.
The handling of conditional branching instructions by prior sequence controllers typically proceeded in a strictly sequential manner: first, the particular status of the data processor to be tested was determined, then, secondly the instruction was decoded and if it was determined to be of a conditional type, then thirdly the branch address was determined depending on the outcome of the test condition. The minimum instruction cycle time is, under this scheme then, the sum of the times for each of these three processes, and since typically the time to produce the test condition signal and to decode the instruction is relatively long, the majority of an instruction cycle is spent awaiting the outcome of the test condition. In effect, the controller is "idling" for most of the instruction processing cycle when an instruction is processed in this strictly sequential manner. Since the microprogram controller instruction cycle time directly determines the microprocessor speed, this "idling" factor measurably degrades this speed.
Previous microprogram sequence controllers have implemented a limited form of multiway branching by permitting certain low-order branch address bits to be modified by "OR"ing them with bits set by various conditional status bits. This approach to multiway branching requires the programmer to assure that any address bit which is not to be modified be "OR"ed only with a zero and is therefore a source of error. This approach also entails a series of two-way branches in which each individual status condition must be tested when a compound status is used as the condition upon which a branch is to take place. Programs implementing multiway branching in this manner are slower and more complex than they need be.
The microinstruction sets utilized previously in microprogram sequence controllers, typically use an ad-hoc format in the assignment of instruction bits coding the instruction type. The sets also promote ad hoc, or unstructured, writing of microprograms. For example, in a typical instruction set, conditional and unconditional microinstructions might be intermingled and the instruction decoding circuitry could not readily make a first-cut categorization of an instruction as conditional. A relatively time-consuming testing of the status condition is required before any instruction can be determined to be unconditional, whereas certain additional functions could be performed by unconditional instructions during the portion of their instruction cycle which would otherwise be used for status testing. Further, the lack of regular microprogram constructs leads to time-consuming program development and debugging and the resulting programs lack the self-documentation of structured programs.